Résumé
Curious learner, good knowledge and passion in Embedded System, looking forward for an industrial position available immediately, where I can be a significant part of the success of an organization by unleashing my development and other skills from an organizational perspective.
Expériences professionnelles
Engineer internship
LCIS Laboratory , Valence - Stage
De Février 2019 à Juillet 2019
• Simulation and Modeling of Faults in a RISC-V Processor.
• Development of Fault Injection platform for a RISC-V processor and Fault Forecasting Analysis.
Software engineer
IVTL Infoview Technologies , Chennai
De Juillet 2016 à Août 2018
• Worked on C, C++, Java, Javascript, SQL, an extensible markup language for designing and developing banking, and HR management secured software.
Research intern
Council of Scientific and Industrial Research , Chennai
De Janvier 2016 à Mars 2016
Worked (in-collaboration with the scientist of CSIR–CEERI–Chennai Mr.Suriya Prakash J) on Robotics & Embedded technology, to grade robot for localization, navigation & mapping for collision analysis.
Formations complémentaires
Master in Integration, Security and Trust in Embedded System
Embedded System
2018 à 2019
• Side channel attacks-Correlation Power Analysis on AES produced by HLS tool named CATAPULT from Mentor Graphics and implemented countermeasures on FPGA Artix-7.
• Developed Precise Fault Injection on RISC-V processor-Rocket core Architecture and Fault forecasting analysis to characterize the effects .
•Design and development of FPGA / Embedded Systems, Reliable Computing, Fault-Tolerant Re-configurable Architecture, Heteroge- neous Embedded Systems or System on Chip, Dependability Issues in Embedded Systems, Test and Verification, Side Channel attacks, Fault attacks and countermeasures.
Bachelor in Engineering
Electronics and Communication
2012 à 2016
•FPGA Design Flow, VHDL, High-Level Synthesis, ARM Neon, System on Chip, Reliability techniques, parallel architecture, Embedded System design, constrained verification, and SystemC, in addition to all standard verification methodology.